1. Technical Field
The present invention relates generally to voltage controlled oscillator (VCO) architectures and more specifically to circuits and methods for linearizing the voltage-to-frequency response of a controlled oscillator.
2. Discussion of the Related Art
The recent growth in wireless communication has increased the demand for more available channels in mobile communication applications, which in turn, has imposed more stringent requirements on the phase noise of local oscillators. In digital applications, phase noise caused by jitter has been addressed. In digital applications, the timing accuracy of the clock signal determines the maximum clock rate at a given supply voltage and hence the maximum number of operations per unit time. Accordingly, clock jitter directly affects timing margins and hence limits system performance.
The most common used architecture for voltage controlled oscillators in complementary metal oxide semiconductor (CMOS) technology is a voltage controlled ring type oscillator. Consisting of several cascaded delay cells, and forming a closed loop that satisfies the well-known Barkhausen Criteria for sustained oscillations, the output frequency is determined by the delay of each cell, which in return is controlled by the control voltage. Delay cell architecture selection has been influenced by noise performance specifications.
It is known that in addition to a circuit's intrinsic noise, there are additional noise sources in the integrated circuit (IC) environment that affect the frequency stability of the oscillator and hence the achievable maximum operation speed. These additional noise sources include, for example, substrate and supply noise arising from switching of digital circuitry. However, short term frequency instabilities of an electrical oscillator are in large part due to inherent device noise, such as, thermal and flicker noise.
It has been shown that the corner in the phase noise spectrum is smaller than noise corner of the oscillator's components by a factor determined by the symmetry properties of the waveform. This result is particularly relevant in metal oxide semiconductor radio frequency (MOS RF) applications because it shows that the effect of inferior MOS device noise, which has been thought to preclude their use in high-performance oscillators, can be reduced by proper design.
Linearization with discrete components, use of switched banks in digitally-controlled oscillators and frequency-locked-loop usage over a VCO to decrease the phase noise and linearize the transfer function are some of the known techniques to overcome VCO non-linearity. However, related design complexity, silicon area, power consumption and possible system instability are some drawbacks associated with these techniques. LC-tank and current mode logic (CML) based VCOs are also used to increase phase noise behavior, but require larger area and more power. Moreover, cross talk between adjacent LC tanks occurs for the VCOs implemented with on-chip inductors.